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this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 1 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 features ? voltage supply: 2.7v ~ 3.6v ? organization - memory cell array : (512m + 16m) x 8bit - data register : (2k + 64) x 8bit ? automatic program and erase - page program : (2k + 64) bytes - block erase : (128k + 4k) bytes ? page read operation - page size : (2k + 64) bytes - random read : 25s (max.) - serial access : 25ns (min.) ? memory cell: 1bit/memory cell ? fast write cycle time - page program time : 250s (typ.) - block erase time : 2ms (typ.) ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions ? reliable cmos floating-gate technology - ecc requirement: 4 bit/512 byte - endurance: 100k program/erase cycles - data retention: 10 years ? command register operation ? automatic page 0 read at power-up option - boot from nand support - automatic memory download ? nop: 4 cycles ? cache program operation for high performance program ? cache read operation ? copy-back operation - edo mode - otp operation - two-plane operation EN27LN4G08 4 gigabit (512m x 8), 3.3 v nand flash memory
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 2 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 general description the device is a 512mx8bit with spare 16mx8bit capacity. the device is offered in 3.3v vcc power supply. its nand cell provides the most cost-effective solution for the solid state mass storage market. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. the device contains 4096 blocks, composed by 64 pages consisting in two nand structures of 32 series connected flash cells. a program operation allows to write the 2112-word page in typical 250us and an erase operation can be performed in typical 2ms on a 128k-byte for x8 device block. data in the page mode can be read out at 25ns cycle time per word. the i/o pins serve as the ports for address and command inputs as well as data input/output. the copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. the cache program feature allo ws the data insertion in the cache register while the data register is copied into the flash array. this pipelined program operation improves the program throughput when long files are written inside the memory. a cache read feature is also implemented. this feature allows to dramatically improving the read throughput when consecutive pages have to be streamed out. this device includes extra feature: automatic read at power up. pin configuration (top view) (tsopi 48l, 12mm x 20mm body, 0.5mm pin pitch) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 nc nc nc nc nc nc ry/b# re# ce# nc nc vcc vss nc nc cle ale we# wp# nc nc nc nc nc nc nc nc nc i/o7 i/o6 i/o5 i/o4 nc nc nc vcc vss nc nc nc i/o3 i/o2 i/o1 i/o0 nc nc nc nc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 standard tsop
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 3 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 table 1. pin description symbol pin name function i/o0 ? i/o7 data inputs/outputs the i/o pins are used to input command, address and data, and to output data during read operations. the i/o pins float to hi-z when the chip is deselected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for commands sent to the command register. commands are latched into the command register through the i/o ports on the rising edge of the we# signal with cle high. ale address latch enable the ale input controls the activating path for address sent to the internal address registers. addresses are latched into the address register through the i/o ports on the rising edge of we# with ale high. ce# chip enable the ce# input is the device selection control. when the device is in the busy state, ce# high is ignored, and the device does not return to standby mode in program or erase operation. regarding ce# control during read operation, refer to ?page read? section of device operation. re# read enable the re# input is the serial data-out control, and when it is low, it active drives the data onto the i/o bus. data is valid t rea after the falling edge of re# which also increments the internal column address counter by one. we# write control the we# input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we# pulse. wp# write protect the wp# pin provides inadvertent program/erase protection during power transitions. the internal high voltage generator is reset when the wp# pin is active low. r/b# ready/busy output the r/b# output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. it is an open drain output and does not float to hi-z condition when the chip is deselected or when outputs are disabled. v cc power supply v cc is the power supply for device. v ss ground nc no connection lead is not internally connected. note: connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected.
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 4 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 block diagram functional block diagram array organization
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 5 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 address cycle map i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 address 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 column address 2nd cycle a8 a9 a10 a11 l* l* l* l* column address 3rd cycle a12 a13 a14 a15 a16 a17 a18 a19 row address 4th cycle a20 a21 a22 a23 a24 a25 a26 a27 row address 5th cycle a28 a29 l* l* l* l* l* l* row address note: 1. column address : starting address of the register. 2. * l must be set to ?low?. 3. * the device ignores any additional input of address cycles than required.
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 6 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 base part number en = eon silicon solution inc. 27ln = 3.0v operation nand flash density 4g = 4gigabit [(512m + 16m) x 8 bit] speed option for burst access time 25 = 25ns temperature range c = commercial (0 to +70 ) i= industrial ( -40 to +85 ) packaging content p = rohs, halogen-free and reach compliant data length 08 = 8-bit width package t = 48-pin tsop ordering information en27ln 4g 08 - 25 t c p
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 7 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 product introduction the device is a 4,224mbit memory organized as 256k rows (pages) by 2,112x8 columns. spare 64x8 columns are located from column address of 2,048~2,111. a 2,112-byte data register is connected to memory cell arrays accommodating data transfer between the i/o buffers and memory during page read and page program operations. the program and read operations are executed on a page basis, while the erase operation is executed on a block basis. the memory array consists of 4096 separately erasable 128k-byte blocks. it indicates that the bit-by-bit erase operation is prohibited on the device. the device has addresses multiplexed into 8 i/os. this scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. command, address and data are all written through i/o's by bringing we# to low while ce# is low. those are latched on the rising edge of we#. command latch enable (cle) and address latch enable (ale) are used to multiplex command and address respectively, via the i/o pins. some commands require one bus cycle. for example, reset command, status read command, etc require just one cycle bus. some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. in addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. command set function 1st cycle 2nd cycle acceptable command during busy read 00h 30h read for copy back 00h 35h read id 90h - reset ffh - o page program 80h 10h copy-back program 85h 10h block erase 60h d0h random data input (1) 85h - random data output (1) 05h e0h read status 70h - o read status 2 f1h - o two-plane read (3) 60h-60h 30h two-plane read for copy-back 60h-60h 35h two-plane random data output (1) (3) 00h-05h e0h two-plane page program (2) 80h-11h 81h-10h two-plane copy-back program (2) 85h-11h 81h-10h two-plane block erase 60h-60h d0h cache program 80h 15h cache read 31h - read start for last page cache read 3fh - two-plane cache read (3) 60h-60h 33h two-plane cache program (2) 80h-11h 81h-15h note: 1. random data input / output can be executed in a page. 2. any command between 11h and 80h/81h/85h is prohibited except 70h/f1h and ffh. 3. two-plane random data output must be used after two-plane read operation or two-plane cache read operation.
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 8 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 absolute maximum ratings parameter symbol rating unit v cc -0.6 to +4.6 v in -0.6 to +4.6 voltage on any pin relative to v ss v i/o -0.6 to vcc + 0.3 (< 4.6) v temperature under bias t bias -40 to +125 storage temperature t stg -65 to +150 short circuit current i os 5 ma note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum ra ting conditions for extended periods may affect reliability. recommended operating conditions (voltage reference to gnd, t a = 0 to 70c or ? 40c to 85c) parameter symbol min. typ. max. unit supply voltage v cc 2.7 3.3 3.6 v supply voltage v ss 0 0 0 v dc and operation characteristics (recommended operating conditions otherwise noted) parameter symbol test conditions min. typ. max. unit page read with serial access i cc1 t rc =25ns, ce# =v il , i out =0ma - 15 30 program i cc2 - - 15 30 operating current erase i cc3 - - 15 30 ma stand-by current (ttl) i sb1 ce# =v ih , wp# =0v/v cc - - 1 ma stand-by current (cmos) i sb2 ce# = v cc -0.2, wp# =0v/ v cc - 10 50 ua input leakage current i li v in =0 to v cc (max) - - 10 ua output leakage current i lo v out =0 to v cc (max) - - 10 ua input high voltage v ih (1) - 0.8 x v cc - v cc +0.3 v input low voltage, all inputs v il (1) - -0.3 - 0.2 x v cc v output high voltage level v oh i oh =-400ua 2.4 - - v output low voltage level v ol i ol =2.1ma - - 0.4 v output low current (r/b#) i ol (r /b#) v ol =0.4v 8 10 - ma note: 1. v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20ns or less. 2. typical value are measured at v cc =3.3v, t a = 25 . and not 100% tested.
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 9 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 valid block symbol min. typ. max. unit n vb 4,016 - 4,096 blocks note: 1. the device may include initial invalid blocks wh en first shipped. the number of valid blocks is presented as first shipped . invalid blocks are defined as blocks that contain one or more bad bits which cause status failure during program and erase operation. do not erase or program factory- marked bad blocks. refer to the attached technical notes for appropriate management of initial invalid blocks. 2. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment and is guaranteed to be a valid block up to 1k program/erase cycles with 4 bit/512 bytes ecc. ac test condition (t a = 0 to 70c or ? 40c to 85c, v cc =2.7v~3.6v, unless otherwise noted) parameter condition input pulse levels 0v to v cc input rise and fall times 5 ns input and output timing levels v cc /2 output load 1 ttl gate and c l =50pf note: refer to read/ busy# section, r/b# output?s busy to ready time is decided by the pull-up resistor (rp) tied to the r/b# pin. capacitance (t a = 25c, v cc =3.3v, f =1.0mhz) item symbol test condition min. max. unit input / output capacitance c i/o v il = 0v - 8 pf input capacitance c in v in = 0v - 8 pf note: capacitance is periodically sampled and not 100% tested. mode selection cle ale ce# we# re# wp# mode h l l h x command input l h l h x read mode address input (5 clock) h l l h h command input l h l h h write mode address input (5 clock) l l l h h data input l l l h x data output x x x x h x during read (busy) x x x x x h during program (busy) x x x x x h during erase (busy) x x (1) x x x l write protect x x h x x 0v/v cc (2) stand-by note: 1. x can be v il or v ih . 2. wp# should be biased to cmos high or cmos low for standby.
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 10 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 program / erase characteristics (t a = 0 to 70c or ? 40c to 85c, v cc =2.7v~3.6v) parameter symbol min. typ. max. unit average program time t prog (1) - 250 750 us dummy busy time for cache program t cbsy (2) - 3 750 us number of partial program cycles in the same page n op - - 4 cycle block erase time t bers - 2 10 ms dummy busy time for two-plane page program t dbsy 0.5 1 us note: 1. typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3v v cc and 25c temperature. 2. t prog is the average program time of all pages. users should be noted that the program time variation from page to page is possible. 3. max. time of t cbsy depends on timing between internal program completion and data in. ac timing characteristics for co mmand / address / data input parameter symbol min. max. unit cle setup time t cls (1) 12 - ns cle hold time t clh 5 - ns ce# setup time t cs 20 - ns ce# hold time t ch 5 - ns we# pulse width t wp 12 - ns ale setup time t als (1) 12 - ns ale hold time t alh 5 - ns data setup time t ds (1) 12 - ns data hold time t dh 5 - ns write cycle time t wc 25 - ns we# high hold time t wh 10 - ns ale to data loading time t adl (2) 70 (2) - ns note: 1. the transition of the corresponding control pins must occur only once while we# is held low. 2. t adl is the time from the we# rising edge of final address cycle to the we# rising edge of first data cycle.
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 11 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 ac characteristics for operation parameter symbol min. max. unit data transfer from cell to register t r - 25 us ale to re# delay t ar 10 - ns cle to re# delay t clr 10 - ns ready to re# low t rr 20 - ns re# pulse width t rp 12 - ns we# high to busy t wb - 100 ns wp# low to we# low (disable mode) wp# high to we# low (enable mode) t ww 100 - ns read cycle time t rc 25 - ns re# access time t rea - 20 ns ce# access time t cea - 25 ns re# high to output hi-z t rhz - 100 ns ce# high to output hi-z t chz - 30 ns ce# high to ale or cle don?t care t csd 0 - ns re# high to output hold t rhoh 15 - ns re# low to output hold t rloh 5 - ns ce# high to output hold t coh 15 - ns re# high hold time t reh 10 - ns output hi-z to re# low t ir 0 - ns re# high to we# low t rhw 100 - ns we# high to re# low t whr 60 - ns read - 5 (1) us program - 10 (1) us erase - 500 us device resetting time during ... ready t rst - 5 (1) us cache busy in read cache (following 31h and 3fh) t dcbsyr - 30 us note: 1. if reset command (ffh) is written at ready state, the device goes into busy for maximum 5us.
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 12 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 nand flash technical notes mask out initial invalid block(s) initial invalid blocks are defined as blocks that contai n one or more initial invalid bits whose reliability is not guaranteed by eon. the information regarding the initial invalid block(s) is called the initial invalid block information. devices with initial invalid block( s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. the system design must be able to mask out the initial invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1k program/erase cycles with 4 bit/512 bytes ecc. identifying initial invalid block(s) and block replacement management unpredictable behavior may result from programming or erasing the defective blocks. figure on next page illustrates an algorit hm for searching factory-mapped defe cts, and the algorit hm needs to be executed prior to any erase or program operations. a host controller has to scan blocks from block 0 to the last block using page read command and check the data at the 1st byte column address in the spare area of the 1st and 2nd page in the block. if the read data is not ffh, the block is interpreted as an invalid block. the initial invalid block information is erasable, and which is impossible to be recovered once it has been erased. therefore, the host controller must be able to recognize the initial invalid block info rmation and to create a corresponding table to manage block replacement upon erase or program error when additional invalid blocks develop with flash memory usage.
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 13 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 14 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 error in write or read operation within its lifetime, the additional invalid blocks may develop with nand flash memory. refer to the qualification report for the actual data. the following possible failu re modes should be considered to implement a highly reliable system. in the case of status read failure after erase or program, block replacement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. in case of read, ecc must be employed. to improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error should be reclaimed by ecc without any block replacement. the block failure rate in the qualification report does not include those reclaimed blocks. failure detection and countermeasure sequence erase failure read status after erase block replacement write program failure read status after program block replacement read up to eight bits failure verify ecc ecc correction ecc : 1. error correcting code --> rs code or bch code etc. 2. example: 4bit correction / 512 bytes program flow chart
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 15 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 erase flow chart read flow chart
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 16 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 block replacement addressing for program operation within a block, the pages must be programmed consecutively from the lsb (least significant bit) page of the block to msb (most significant bit) pages of the block. random page address programming is prohibited. in this case, the definition of lsb page is the lsb among the pages to be programmed. therefore, lsb page doesn?t need to be page 0. (64) (32) (3) (2) (1) : : page 63 page 31 page 2 page 1 page 0 data register from the lsb page to msb page d a t a in: data (1) data (64) (64) (1) (3) (32) (2) : : page 63 page 31 page 2 page 1 page 0 data register ex.) random page program (prohibition) d a t a in: data ( 1 ) data ( 64 )
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 17 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 system interface using ce# don?t-care for an easier system interface, ce# may be inactive during the data-loading or serial access as shown below. the internal 2,112 bytes page registers are utilized as separate buffers for this operation and the system design gets more flexible. in addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating ce# during the data-loading and reading would provide significant savings in power consumption. program / read operation with ? ce# don?t-care ? address information i/o data address i/ox data in / out col. add1 col. add2 row add1 row add2 row add3 i/o0~7 2112 bytes a0 ~ a7 a8 ~ a11 a12 ~ a19 a20 ~ a27 a28 ~ a29
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 18 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 command latch cycle address latch cycle
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 19 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 input data latch cycle serial access cycle after read (cle = l, ale = l, we# = h) note: 1. dout transition is measured at 200mv from steady state voltage with load. 2. t rhoh starts to be valid when frequency is lower than 33mhz.
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 20 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 serial access cycle after read (edo type cle = l, ale = l, we# = h) note: 1. transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 2. t rloh is valid when frequency is higher than 33mhz. t rhoh starts to be valid when frequency is lower than 33mhz. status read cycle
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 21 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 read operation (read one page) read operation (intercepted by ce#)
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 22 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 random data output in a page page program operation
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 23 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 page program operation with random data input note: t adl is the time from we# rising edge of final address cycle to the we# rising edge of first data cycle. copy-back program operation with random data input
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 24 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 cache program operation cache read operation
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 25 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 block erase operation
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 26 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 read id operation two-plane page read operation with two-plane random data out
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 27 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 two-plane cache read operation
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 28 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 note: 1. the column address will be rese t to 0 by the 3fh command input. 2. cache read operation is available only within a block. 3. make sure to terminate the operation with 3fh command. if the operation is terminated by 31h command, monitor i/o6 (ready/busy) by issuing status read command (70h) and make sure the previous page read operation is completed. if the page read operation is completed, issue ffh reset before next operation.
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 29 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 two-plane page program operation
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 30 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 two-plane cache program operation two-plane block erase operation
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 31 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 id definition table id access command = 90h maker code device code 3 rd cycle 4 th cycle 5 th cycle c8h dch 90h 95h 54h description 1 st byte maker code 2 nd byte device code 3 rd byte internal chip number, cell type, number of simultaneously programmed pages, etc. 4 th byte page size, block size, redundant area size, organization, serial access minimum 5 th byte plane number, plane size 3rd id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1 0 0 2 0 1 4 1 0 internal chip number 8 1 1 2 level cell 0 0 4 level cell 0 1 8 level cell 1 0 cell type 16 level cell 1 1 1 0 0 2 0 1 4 1 0 number of simultaneously programmed page 8 1 1 not support 0 interleave program between multiple chips support 1 not support 0 cache program support 1
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 32 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 4th id data descriptio n i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1kb 0 0 2kb 0 1 4kb 1 0 page size (w/o redundant area) 8kb 1 1 8 0 redundant area size (byte/512byte) 16 1 64kb 0 0 128kb 0 1 256kb 1 0 block size (w/o redundant area) 512kb 1 1 x8 0 organization x16 1 45ns 0 0 reserved 0 1 25ns 1 0 serial access time reserved 1 1 5th id data descriptio n i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1 0 0 2 0 1 4 1 0 plane number 8 1 1 64mb 0 0 0 128mb 0 0 1 256mb 0 1 0 512mb 0 1 1 1gb 1 0 0 2gb 1 0 1 4gb 1 1 0 plane size (w/o redundant area) 8gb 1 1 1 reserved reserved 0 0 0
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 33 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 device operation page read upon initial device power up, the device defaults to read mode. this operation is also initiated by writing 00h command, five-cycle address, and 30h command. after initial power up, the 00h command can be skipped because it has been latched in the command register. the 2,112byte of data on a page are transferred to cache registers via data registers within 25us (t r ). host controller can detect the completion of this data transfer by checking the r/b# output. once data in the selected page have been loaded into cache registers, each byte can be read out in 25ns cycle time by continuously pulsing re# . the repetitive high-to-low transitions of re# clock signal make the device output data starting from the designated column address to the last column address. the device can output data at a random column address instead of sequential column address by using the random data output command. random data output command can be executed multiple times in a page. after power up, device is in read mode so 00h command cycle is not necessary to start a read operation. a page read sequence is illustrated in the following figure, where co lumn address, page address are placed in between commands 00h and 30h. after t r read time, the r/b# de-asserts to ready state. read status command (70h) can be issued right after 30h. host controller can toggle re# to access data starting with the designated column address and their successive bytes. read operation
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 34 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 random data output in a page
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 35 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 page program the device is programmed based on the unit of a page, and consecutive partial page programming on one page without intervening erase operation is strictly prohibited. addressing of page program operations within a block should be in sequential order. a complete page program cycle consists of a serial data input cycle in which up to 2,112byte (1,056word) of data can be loaded into data register via cache register, followed by a programming period during which the loaded data are programmed into the designated memory cells. the serial data input cycle begins with the serial data input command (80h), followed by a five-cycle address input and then serial data loading. the bytes not to be programmed on the page do not need to be loaded. the column address for the next data can be changed to the address follows random data input command (85h). random data input command may be repeated multiple times in a page. the page program confirm command (10h) starts the programming process. writing 10h alone without entering data will not initiate the programming proc ess. the internal write engine automatically executes the corresponding algorithm and controls timing for programming and verification, thereby freeing the host controller for other tasks. once the program process starts, the host controller can detect the completion of a program cycle by monitoring the r/b# output or reading the status bit (i/o6) using the read status command. only read status and reset commands are valid during programming. when the page program operation is completed, the host controller can check the status bit (i/o0) to see if the page program operation is successfully done. the command register remains the read status mode unless another valid co mmand is written to it. a page program sequence is illustrated in following fi gure, where column addres s, page address, and data input are placed in between 80h and 10h. after t prog program time, the r/b# de-asserts to ready state. read status command (70h) can be issued right after 10h. program & read status operation random data input in a page
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 36 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 cache program cache program is an extension of page program, which is executed with 2,112 byte (x8) data registers, and is available only within a block. since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell. after writing the first set of data up to 2,112 bytes (x8) into the selected cache registers, cache program command (15h) instead of actual page program (10h) is inputted to make cache registers free and to start internal program operation. to transfer data from cache registers to data registers, the device remains in busy state for a short period of time (t cbsy ) and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data registers. read status command (70h) may be issued to find out when cache registers become ready by polling the cache-busy status bit (i/o6). pass/fail status of only the previous page is available upon the return to ready state. when the next set of data is inputted with the cache program command, t cbsy is affected by the progress of pending internal programming. the programming of the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. the status bit (i/o5) for internal ready/busy may be polled to identity the completion of internal programming. if the system monitors the progress of programming only with r/b#, the last page of the target programming sequence must be programmed with actual page program command (10h). cache program (available only within a block) note: 1. since programming the last page does not employ caching, the program time has to be that of page program. however, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula. 2. t prog = program time for the last page + program time for the (last-1)th page ? (program command cycle time + last page data loading time)
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 37 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 copy-back program copy-back program is designed to efficiently copy data stored in memory cells without time-consuming data reloading when there is no bit error detected in the stored data. the benefit is particularly obvious when a portion of a block is updated and the rest of the block needs to be copied to a newly assigned empty block. copy-back operation is a sequential execution of read for copy-back and of copy-back program with destination address. a read for copy-back operation with ?35h? command and the source address moves the whole 2,112 byte data into the internal buffer. the host controller can detect bit errors by sequentially reading the data output. copy-back program is initiated by issuing page-copy data-input command (85h) with destination address. if data modification is necessary to correct bit errors and to avoid error propagation, data can be reloaded after the destination address. data modification can be repeated multiple times as shown in the following figure. actual programming operation begins when program confirm command (10h) is issued. once the program process starts, the read status command (70h) may be entered to read the status register. the host controller can detect the completion of a program cycle by monitoring the r/b# output, or the status bit (i/o6) of the status register. when the copy-back program is complete, the status bit (i/o0) may be checked. the command register remains read status mode un til another valid command is written to it. page copy-back program operation page copy-back program operation with random data input
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 38 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 block erase the block-based erase operation is initiated by an erase setup command (60h), followed by a three- cycle row address, in which only plane address and block address are valid while page address is ignored. the erase confirm command (d0h) following the row address starts the internal erasing process. the two-step command sequence is designed to prevent memory content from being inadvertently changed by external noise. at the rising edge of we# after the erase confirm command input, the internal control logic handles erase and erase-verify. when the erase operation is completed, the host controller can check status bit (i/o0) to see if the erase operation is successfully done. the following figure illustrates a block erase sequence, and the address input (the first page address of the selected block) is placed in between commands 60h and d0h. after t berase erase time, the r/b# de-asserts to ready state. read status command (70h) can be issued right after d0h to check the execution status of erase operation. block erase operation one-time programmable (otp) operations this eon flash device offers one-time programmable memory area. thirty full pages of otp data are available on the device, and the entire range is guaranteed to be good. the otp area is accessible only through the otp commands. the otp area leaves the factory in an unwritten state. the otp area cannot be erased, whether it is protected or not. protecting the otp area prevents further programming of that area. the otp area is only accessible while in otp operation mode. to set the device to otp operation mode, issue the set feature (efh-90h-01h) command. when the device is in otp operation mode, subsequent read and/or page program are applied to the otp area. when you want to come back to normal operation, you need to use efh-90h-00h for otp mode release. otherwise, device will stay in otp mode. to program an otp page, issue the serial data input (80h) command followed by 5 address cycles. the first two address cycles are column address that must be set as 00h. for the third cycle, select a page in the range of 00h through 1dh. the fourth and fifth cycle is fixed at 00h. next, up to 2,112 bytes of data can be loaded into data register. the bytes other than those to be programmed do not need to be loaded. random data input (85h) command in this device is prohibited. the page program confirms (10h) command initiates the programming process. the internal control logic automatically executes the programming algorithm, timing and verification. please note that no partial-page program is allowed in the otp area. in addition, the otp pages must be programmed in the ascending order. a programmed otp page will be automatically protected . similarly, to read data from an otp page, set the device to otp operation mode and then issue the read (00h-30h) command. the first two address cycles are column address that must be set as 00h and random data output (05h-e0h) command is prohibited as well. all pages in the otp area will be protected simult aneously by issuing the set feature (efh-90h-03h)
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 39 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 command to set the device to otp protection mode. after the otp area is protected, no page in the area is programmable and the whole area cannot be unprotected. the read status (70h) command is the only valid command for reading status in otp operation mode. table 2. otp modes and commands set feature command read efh-90h 1 -01h 2 00h-30h otp operation mode page program efh-90h-01h 80h-10h otp protection mode program protect efh-90h-03h 80h-10h otp release mode leave otp mode efh-90h-00h note: 1. 90h is otp status register address. 2. 00h, 01h, and 03h are otp status register data values. table 3. otp area details description value number of otp pages 30 otp pages address 00h ? 1dh number of partial page programs for each page in the otp area 1 read status a status register on the device is used to check whether program or erase operation is completed and whether the operation is completed successfully. after writing 70h/f1h command to the command register, a read cycle outputs the content of the status register to i/o pins on the falling edge of ce# or re#, whichever occurs last. these two commands allow the system to poll the progress of each device in multiple memory connections even when r/b# pins are common-wired. re# or ce# does not need to toggle for status change. the command register remains in read status mode unless other commands are issued to it. therefore, if the status register is read during a random read cycle, a read command (00h) is needed to start read cycles.
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 40 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 status register definition for 70h command i/o page program block erase read cache read definition i/o0 pass / fail pass / fail not use not use pass: ?0? fail: ?1? i/o1 not use (pass/fail, otp) not use not use not use don?t cared i/o2 not use not use not use not use don?t cared i/o3 not use not use not use not use don?t cared i/o4 not use not use not use not use don?t cared i/o5 not use not use not use true ready / busy busy: ?0? ready: ?1? i/o6 ready / busy ready / busy ready / busy ready / busy busy: ?0? ready: ?1? i/o7 write protect write protect write protect write protect protected: ?0? not protected: ?1? status register definition for f1h command i/o page program block erase cache program read cache read definition i/o0 chip pass / fail chip pass / fail chip pass / fail (n) not use not use pass: ?0? fail: ?1? i/o1 plane0 pass / fail plane0 pass / fail plane0 pass / fail (n) not use not use pass: ?0? fail: ?1? i/o2 plane1 pass / fail plane1 pass / fail plane1 pass / fail (n) not use not use pass: ?0? fail: ?1? i/o3 not use not use plane0 pass / fail (n-1) not use not use pass: ?0? fail: ?1? i/o4 not use not use plane1 pass / fail (n-1) not use not use pass: ?0? fail: ?1? i/o5 not use not use true ready / busy not use true ready / busy busy: ?0? ready: ?1? i/o6 ready / busy ready / busy ready / busy ready / busy ready / busy busy: ?0? ready: ?1? i/o7 write protect write protect write protect write protect write protect protected: ?0? not protected: ?1? note: 1. i/os defined na are recommended to be masked out when read status is being executed. 2. n : current page, n-1 : previous page.
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 41 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. four read cycles sequentially output the manufacturer code (c8h), and the device code and 3rd, 4th, 5th cycle id respectively. the command register remains in read id mode until further commands are issued to it. read id operation id definition table id access command = 90h 1 st cycle maker code 2 nd cycle device code 3 rd cycle 4 th cycle 5 th cycle c8h dch 90h 95h 54h description 1 st byte maker code 2 nd byte device code 3 rd byte internal chip number, cell type, number of simultaneously programmed pages, etc. 4 th byte page size, block size, redundant area size, organization, serial access minimum 5 th byte plane number, plane size
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 42 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during random read, program or er ase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp# is high. if the device is already in reset state a new reset command will be accepted by the command register. the r/b# pin changes to low for t rst after the reset command is written. re fer to the following figure. device status after power-up after reset operation mode 00h command is latched waiting for next command cache read cache read is an extension of page read, and is available only within a block. the normal page read command (00h-30h) is always issued before invoking cache read. after issuing the cache read command (31h), read data of the designated page (page n) are transferred from data registers to cache registers in a short time period of t dcbsyr , and then data of the next page (page n+1) is transferred to data registers while the data in the cache registers are being read out. host controller can retrieve continuous data and achieve fast read performance by iterating cache read operation. the read start for last page cache read command (3fh) is used to complete data transfer from memory cells to data registers. read operation with cache read
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 43 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 two-plane page read two-plane page read is an extension of page read, for a single plane with 2,112 byte data registers. since the device is equipped with two memory planes, activating the two sets of 2,112 byte data registers enables a random read of two pages. two-plane page read is initiated by repeating command 60h followed by three address cycles twice. in this case, only same page of same block can be selected from each plane. after read confirm command (30h) the 4,224 bytes of data within the selected two page are transferred to the cache registers via data registers in less than 25us (t r ). the system controller can detect the completion of data transfer (t r ) by monitoring the output of r/b# pin. once the data is loaded into the cache registers, the data output of first plane can be read out by issuing command 00h with five address cycles, command 05h with two column address and finally e0h. the data output of second plane can be read out using the identical command sequences.
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 44 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 two-plane cache read two-plane cache read is an extension of cache read, for a single plane with 2,112 byte data registers. since the device is equipped with two memory planes, the two sets of 2,112 byte data registers enables a cache read of two pages. two-plane cache read is initiated by repeating command 60h followed by three address cycles twice. in this case only same page of same block can be selected from each plane. after read confirm command (33h) the 4,224 bytes of data within the selected two page are transferred to the cache registers via data registers in less than 25us (t r ). after issuing cache read command (31h), read data in the data registers is transferred to cache registers for a short period of time (t dbsy ). once the data is loaded into the cache registers from data registers, the data output of first plane can be read out by issuing command 00h with five address cycles, command 05h with two column address and finally e0h. the data output of second plane can be read out using the identical command sequences.
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 45 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 two-plane page program two-plane page program is an extension of page program, for a single plane with 2,112 byte data registers. since the device is equipped with two memory planes, activating the two sets of 2112 byte data registers enables a simultaneous programming of two pages. after writing the first set of data up to 2,112 byte into the selected data registers via cache registers, dummy page program command (11h) instead of actual page program command (10h) is inputted to finish data-loading of the first plane. since no programming process is involved, r/b# remains in busy state for a short period of time (t dbsy ). read status command (70h) may be issued to find out when the device returns to ready state by polling the r/b status bit (i/o 6). then the next set of data for the other plane is inputted after 81h command and address sequences. after inputting data for the last page, actual true page program (10h) instead of dummy page program command (11h) must be followed to start the programming process. the operation of r/b and read status is the same as that of page program. although two planes are programmed simultaneously, pass/fail is not available for each page when the program operation completes. status bit of i/o 0 is set to ?1? when any of the pages fails.
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 46 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 two-plane copy-back program two-plane copy-back program is an extension of copy-back program, for a single plane with 2,112 byte data registers. since the device is equipped with two memory planes, activating the two sets of 2,112 byte data registers enables a simultaneous programming of two pages. two-plane copy-back program
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 47 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 two-plane copy-back program with random data input
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 48 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 two-plane cache program two-plane cache program is an extension of cache program, for a single plane with 2,112 byte data registers. since the device is equipped with two memory planes, activating the two sets of 2,112 byte data registers enables a simultaneous programming of two pages. note: 1. it is noticeable that same row address except for a20 is applied to the two blocks 2. any command between 11h and 81h is prohibited except 70h/f1h and ffh. 3. since programming the last page does not employ caching, the program time has to be that of page program. however, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula. tprog = program time for the last page + program time for the (last ? 1) th page ? (program command cycle time + last page data loading time)
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 49 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 two-plane block erase basic concept of two-plane block erase operation is identical to that of two-plane page program. up to two blocks, one from each plane can be simultaneously erased. standard block erase command sequences (block erase setup command 60h followed by three address cycles) may be repeated up to twice for erasing up to two blocks. only one block should be selected from each plane. the erase confirm command (d0h) initiates the actual erasing process. the completion is detected by monitoring r/b pin or ready/busy status bit (i/o 6). ready/busy# the device has an r/b# output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/b# pin is normally high but transition to low after program or erase command is written to the command register or random read is started after address loading. it returns to high when the internal controller has finished the operation. the pin is an open- drain driver thereby allowing two or more r/b# outputs to be or-tied. because pull-up resistor value is related to tr (r/b#) and current drain during busy (ibusy), an appropriate value can be obtained with the following reference chart (t he following figure). its value can be determined by the following guidance. read / busy pin electrical specifications
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 50 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 r p vs t rhoh vs c l r p value guidance where i l is the sum of the input currents of all devices tied to the r/ b# pin. r p (max) is determined by maximum permissible limit of tr data protection & power-up sequence the timing sequence shown in the following figure is necessary for the power-on/off sequence. the device internal initialization starts after the powe r supply reaches an appropriate level in the power on sequence. during the initialization the device r/b# signal indicates the busy state as shown in the following figure. in this time period, the acceptable commands are 70h. the wp# signal is useful for protecting against data corruption at power on/off. ac waveforms for power transition
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 51 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 write protect operation enable wp# during erase and program busy is prohibited. the erase and program operations are enabled and disable as follows. program enable mode: note: wp# keeps ?high? until programming finish program disable mode:
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 52 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 erase enable mode: note: wp# keeps ?high? until erasing finish erase disable mode:
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 53 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 package dimension 48l tsop 12mm x 20mm package outline
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 54 EN27LN4G08 rev. a, issue date: 2013 / 10 / 03 revisions list revision no description date a initial release 2013/01/23 b 1. update ordering information ? p = rohs, halogen-free and reach compliant ? on page 6. 2. add one-time programmable (otp) operations description. 2013/10/03

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